What we do
01
Learn digital design
CMOS gates, flip flops, FSMs, and basic Verilog
02
Write RTL
Design your circuit in SystemVerilog, module by module
03
Verify
Write cocotb testbenches, simulate with Icarus Verilog
04
Synthesize
Yosys maps RTL to IHP standard cells
05
Place & route
OpenROAD places cells and routes metal layers
06
Tape out
Submit GDS to Tiny Tapeout for fabrication
Gallery
GDS layout
tt_um_cwru_cpu · IHP 130nm · 1866 cells
GDS render
3D view · Tiny Tapeout viewer
FPGA demo
Basys3 · fibonacci sequence · 7-seg display
Prerequisites
Basic programming experience
Any language is fine — Python, C, Java. You just need to be comfortable reading and writing code.
Digital logic fundamentals (learnable here)
AND/OR/NOT gates, flip flops, combinational vs sequential logic. Resources below will get you there.
Curiosity about how hardware actually works
The best motivation is genuinely wanting to understand what's happening inside a chip.
Learning path
Digital logic basics week 1–2
Boolean algebra, logic gates, truth tables, timing diagrams. HDLBits exercises 1–20 are a great starting point.
Verilog / SystemVerilog week 2–4
Modules, wire vs reg, always blocks, combinational vs clocked logic. Complete HDLBits through the sequential circuits section.
Computer architecture week 3–5
Instruction sets, datapaths, ALUs, register files. Patterson & Hennessy Ch. 1–4 or Nand2Tetris Part II both work well.
RISC-V ISA (optional but useful) week 4–6
R/I/S/B/U/J instruction formats and encoding. Useful if you want to implement a processor, but not required for all ASIC designs.
Tiny Tapeout + OpenLane flow week 6–8
Set up the TT template, wire up your design, run the GDS CI pipeline, and submit. The TT docs are excellent.
ASICWRU handbook
The ASICWRU Handbook
A comprehensive, personally written reference covering everything you need to go from zero to tapeout. Every article is written by club members who've been through the flow — not copy-pasted from a textbook.
github.com/AxC1271/ASICWRU-Handbook →
external resources worth knowing alongside the handbook
interactive exercises
HDLBits
200+ browser-based Verilog exercises from basic gates to pipelined CPUs. Best hands-on complement to the handbook.
hdlbits.01xz.net →
tapeout platform
Tiny Tapeout
The platform we use to submit designs to silicon. Excellent documentation, starter templates, and an active Discord community.
tinytapeout.com →
course
Nand2Tetris
Build a computer from NAND gates up. Great companion to the computer architecture section of the handbook.
nand2tetris.org →
Project ideas for next tapeout
A CPU is the classic first project — but it doesn't have to be yours. Here are some ideas spanning different difficulty levels and interests.
beginner
UART controller
Implement TX/RX serial communication. Very concrete, great first project — you can test it talking to your laptop.
FSMserial
beginner
PWM generator
Configurable pulse-width modulator with duty cycle control. Hook it up to an LED or servo for a satisfying demo.
countercomparator
beginner
LFSR random number generator
Hardware pseudorandom number generator using a linear feedback shift register. Surprisingly fun to characterize.
shift regXOR
intermediate
Custom ISA processor
Design your own instruction set from scratch. Fewer constraints than RISC-V — great for exploring ISA design tradeoffs.
datapathcontrol
intermediate
FIR filter
Fixed-point digital signal processing. Useful for audio and sensor fusion, and great for learning pipelined multipliers.
DSPfixed-point
intermediate
VGA signal generator
Drive a monitor directly from your chip — pixel timing, sync pulses, and a framebuffer. Extremely satisfying when it works.
timingmemory
advanced
AES encryption block
Hardware implementation of AES-128. A great introduction to cryptographic hardware and side-channel considerations.
cryptoS-box
advanced
Dot product engine
A systolic array for matrix multiply — the core of every neural network accelerator. Build the thing that runs AI.
systolicMAC
advanced
Pipelined RISC-V
Extend the club's single-cycle RV32I to a 5-stage pipeline with hazard detection and forwarding. A natural next step.
pipelinehazards
Our first tapeout — RV32I CPU
Single-cycle RV32I processor in SystemVerilog
Full ALU, 32-register file, immediate generator, control unit, branch/jump logic. Verified with cocotb running fibonacci.
1866 standard cells — 36% tile utilization on a 2×2 tile
IHP SG13G2 130nm process. Critical path ~4.7ns. Estimated max frequency ~150MHz at typical corner.
2.95mW total at nominal conditions (1.2V, 25°C)
64% sequential, 21% clock tree, 15% combinational logic. Register file dominates power as expected.
Zero setup violations across all process corners
+11.6ns worst-case setup slack at slow corner (1.08V, 125°C). Clean timing closure across all corners.
Alumni
AC
Andrew Chen
ASIC Design Lead
Led the club's first tapeout including a full RV32I processor on IHP 130nm. MS ECE at Carnegie Mellon (Integrated Systems), starting Aug 2026.
Get involved
Join our Discord
The best place to ask questions, get help with your design, and stay up to date on what the club is working on.
discord.gg/4qHSxRcE →
Star us on GitHub
Check out the source for our first tapeout — the full RTL, testbenches, and GDS flow are all open source.
github.com/AxC1271/CWRU_CPU →
Email us
Interested in joining, collaborating, or just want to learn more? Reach out directly and we'll get back to you.
chips@case.edu →
Show up
We meet regularly during the semester. No experience required — just bring curiosity. Look for us through CWRU CHIPS.
meetings via CWRU CHIPS